Motorola MC6809


Instruction Set

A good overview about the Motorlola MC6809 can be found on the MC6809 wiki page. A good detailed and well structured overview of the instruction set can be found in this 6X09 Instruction Sets manual. It describes both the Motorola 6809 and Hitachi 6309, which has more registers and instructions and also an 6809 emulation mode.

Undocumented Instructions

The support of undocumented MC6809 instructions can be controlled either with the command line option -u, with the menu item Processor->Undocumented Instructions or in the user settings. To be able do distinguish them from the supported instructions the disassembler displays their mnemonics in lower case. Undocumented MC6809 instructions are not available with Fastflex.

They have been found empirically so they may not be reliable, incomplete or may work on some MC6809 chips but not on others. Motorola never published any information about undefined opcodes.

The following undocumented instructions are supported by flexemu:

Mnemonic Opcode Mode Description
neg 01 Direct Same as Op 00 (NEG)
negcom 02 Direct If cc.c = 0 then NEG else COM
lsr 05 Direct Same as Op 04 (LSR)
dec 0B Direct Same as Op 0A (DEC)
reset 3E Inherent Same as CPU Reset
nega 41 Inherent Same Op 40 (NEGA)
coma 42 Inherent Same Op 43 (COMA)
lsra 45 Inherent Same Op 44 (LSRA)
deca 4B Inherent Same Op 4A (DECA)
clra 4E Inherent Same Op 4F (CLRA)
negb 51 Inherent Same Op 50 (NEGB)
comb 52 Inherent Same Op 53 (COMB)
lsrb 55 Inherent Same Op 54 (LSRB)
decb 5B Inherent Same Op 5A (DECB)
clrb 5E Inherent Same Op 5F (CLRB)
neg 61 Indexed Same Op 60 (NEG)
com 62 Indexed Same Op 63 (COM)
lsr 65 Indexed Same Op 64 (LSR)
dec 6B Indexed Same Op 6A (DEC)
neg 71 Extended Same Op 70 (NEG)
com 72 Extended Same Op 73 (COM)
lsr 75 Extended Same Op 74 (LSR)
dec 7B Extended Same Op 7A (DEC)
EXG 1E Implied In extension to the normal exchange of Byte and Word registers also exchange of mixed Byte/Word registers is supported. If the target is a Word the upper Byte is filled with $FF. If the target is a Byte only the lower Byte of the source register is moved.

Also supports "invalid" register codes. If the source is such an invalid register $FF or $FFFF is moved to the target register

TFR 1F Implied In extension to the normal transfer of Byte and Word registers also transfer of mixed Byte/Word registers is supported. If the target is a Word the upper Byte is filled with $FF. If the target is a Byte only the lower Byte of the source register is moved.

Also supports "invalid" register codes. If the source is such an invalid register $FF or $FFFF is moved to the target register

SEE ALSO

Documents on the behalf of the FLEX User Group

Related Links