SAM3U DMAC

DMA Controller (DMAC) User Interface

Registers

Register Mapping
Address Register Name Access Reset
0x400B0000 DMAC Global Configuration Register DMAC_GCFG read-write 0x00000010
0x400B0004 DMAC Enable Register DMAC_EN read-write 0x00000000
0x400B0008 DMAC Software Single Request Register DMAC_SREQ read-write 0x00000000
0x400B000C DMAC Software Chunk Transfer Request Register DMAC_CREQ read-write 0x00000000
0x400B0010 DMAC Software Last Transfer Flag Register DMAC_LAST read-write 0x00000000
0x400B0018 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register. DMAC_EBCIER write-only -
0x400B001C DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register. DMAC_EBCIDR write-only -
0x400B0020 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register. DMAC_EBCIMR read-only 0x00000000
0x400B0024 DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register. DMAC_EBCISR read-only 0x00000000
0x400B0028 DMAC Channel Handler Enable Register DMAC_CHER write-only -
0x400B002C DMAC Channel Handler Disable Register DMAC_CHDR write-only -
0x400B0030 DMAC Channel Handler Status Register DMAC_CHSR read-only 0x00FF0000
0x400B003C DMAC Channel Source Address Register (ch_num = 0) DMAC_SADDR0 read-write 0x00000000
0x400B0040 DMAC Channel Destination Address Register (ch_num = 0) DMAC_DADDR0 read-write 0x00000000
0x400B0044 DMAC Channel Descriptor Address Register (ch_num = 0) DMAC_DSCR0 read-write 0x00000000
0x400B0048 DMAC Channel Control A Register (ch_num = 0) DMAC_CTRLA0 read-write 0x00000000
0x400B004C DMAC Channel Control B Register (ch_num = 0) DMAC_CTRLB0 read-write 0x00000000
0x400B0050 DMAC Channel Configuration Register (ch_num = 0) DMAC_CFG0 read-write 0x01000000
0x400B0064 DMAC Channel Source Address Register (ch_num = 1) DMAC_SADDR1 read-write 0x00000000
0x400B0068 DMAC Channel Destination Address Register (ch_num = 1) DMAC_DADDR1 read-write 0x00000000
0x400B006C DMAC Channel Descriptor Address Register (ch_num = 1) DMAC_DSCR1 read-write 0x00000000
0x400B0070 DMAC Channel Control A Register (ch_num = 1) DMAC_CTRLA1 read-write 0x00000000
0x400B0074 DMAC Channel Control B Register (ch_num = 1) DMAC_CTRLB1 read-write 0x00000000
0x400B0078 DMAC Channel Configuration Register (ch_num = 1) DMAC_CFG1 read-write 0x01000000
0x400B008C DMAC Channel Source Address Register (ch_num = 2) DMAC_SADDR2 read-write 0x00000000
0x400B0090 DMAC Channel Destination Address Register (ch_num = 2) DMAC_DADDR2 read-write 0x00000000
0x400B0094 DMAC Channel Descriptor Address Register (ch_num = 2) DMAC_DSCR2 read-write 0x00000000
0x400B0098 DMAC Channel Control A Register (ch_num = 2) DMAC_CTRLA2 read-write 0x00000000
0x400B009C DMAC Channel Control B Register (ch_num = 2) DMAC_CTRLB2 read-write 0x00000000
0x400B00A0 DMAC Channel Configuration Register (ch_num = 2) DMAC_CFG2 read-write 0x01000000
0x400B00B4 DMAC Channel Source Address Register (ch_num = 3) DMAC_SADDR3 read-write 0x00000000
0x400B00B8 DMAC Channel Destination Address Register (ch_num = 3) DMAC_DADDR3 read-write 0x00000000
0x400B00BC DMAC Channel Descriptor Address Register (ch_num = 3) DMAC_DSCR3 read-write 0x00000000
0x400B00C0 DMAC Channel Control A Register (ch_num = 3) DMAC_CTRLA3 read-write 0x00000000
0x400B00C4 DMAC Channel Control B Register (ch_num = 3) DMAC_CTRLB3 read-write 0x00000000
0x400B00C8 DMAC Channel Configuration Register (ch_num = 3) DMAC_CFG3 read-write 0x01000000
0x400B01E4 DMAC Write Protect Mode Register DMAC_WPMR read-write 0x00000000
0x400B01E8 DMAC Write Protect Status Register DMAC_WPSR read-only 0x00000000

Register Fields

DMAC DMAC Global Configuration Register

Name: DMAC_GCFG

Access: read-write

Address: 0x400B0000

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - ARB_CFG - - - -

DMAC DMAC Enable Register

Name: DMAC_EN

Access: read-write

Address: 0x400B0004

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - ENABLE

DMAC DMAC Software Single Request Register

Name: DMAC_SREQ

Access: read-write

Address: 0x400B0008

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
DSREQ3 SSREQ3 DSREQ2 SSREQ2 DSREQ1 SSREQ1 DSREQ0 SSREQ0

DMAC DMAC Software Chunk Transfer Request Register

Name: DMAC_CREQ

Access: read-write

Address: 0x400B000C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
DCREQ3 SCREQ3 DCREQ2 SCREQ2 DCREQ1 SCREQ1 DCREQ0 SCREQ0

DMAC DMAC Software Last Transfer Flag Register

Name: DMAC_LAST

Access: read-write

Address: 0x400B0010

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
DLAST3 SLAST3 DLAST2 SLAST2 DLAST1 SLAST1 DLAST0 SLAST0

DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Enable register.

Name: DMAC_EBCIER

Access: write-only

Address: 0x400B0018

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - ERR3 ERR2 ERR1 ERR0
15 14 13 12 11 10 9 8
- - - - CBTC3 CBTC2 CBTC1 CBTC0
7 6 5 4 3 2 1 0
- - - - BTC3 BTC2 BTC1 BTC0

DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer Transfer Completed Interrupt Disable register.

Name: DMAC_EBCIDR

Access: write-only

Address: 0x400B001C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - ERR3 ERR2 ERR1 ERR0
15 14 13 12 11 10 9 8
- - - - CBTC3 CBTC2 CBTC1 CBTC0
7 6 5 4 3 2 1 0
- - - - BTC3 BTC2 BTC1 BTC0

DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Mask Register.

Name: DMAC_EBCIMR

Access: read-only

Address: 0x400B0020

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - ERR3 ERR2 ERR1 ERR0
15 14 13 12 11 10 9 8
- - - - CBTC3 CBTC2 CBTC1 CBTC0
7 6 5 4 3 2 1 0
- - - - BTC3 BTC2 BTC1 BTC0

DMAC DMAC Error, Chained Buffer Transfer Completed Interrupt and Buffer transfer completed Status Register.

Name: DMAC_EBCISR

Access: read-only

Address: 0x400B0024

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - ERR3 ERR2 ERR1 ERR0
15 14 13 12 11 10 9 8
- - - - CBTC3 CBTC2 CBTC1 CBTC0
7 6 5 4 3 2 1 0
- - - - BTC3 BTC2 BTC1 BTC0

DMAC DMAC Channel Handler Enable Register

Name: DMAC_CHER

Access: write-only

Address: 0x400B0028

31 30 29 28 27 26 25 24
- - - - KEEP3 KEEP2 KEEP1 KEEP0
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - SUSP3 SUSP2 SUSP1 SUSP0
7 6 5 4 3 2 1 0
- - - - ENA3 ENA2 ENA1 ENA0

DMAC DMAC Channel Handler Disable Register

Name: DMAC_CHDR

Access: write-only

Address: 0x400B002C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - RES3 RES2 RES1 RES0
7 6 5 4 3 2 1 0
- - - - DIS3 DIS2 DIS1 DIS0

DMAC DMAC Channel Handler Status Register

Name: DMAC_CHSR

Access: read-only

Address: 0x400B0030

31 30 29 28 27 26 25 24
- - - - STAL3 STAL2 STAL1 STAL0
23 22 21 20 19 18 17 16
- - - - EMPT3 EMPT2 EMPT1 EMPT0
15 14 13 12 11 10 9 8
- - - - SUSP3 SUSP2 SUSP1 SUSP0
7 6 5 4 3 2 1 0
- - - - ENA3 ENA2 ENA1 ENA0

DMAC DMAC Channel Source Address Register (ch_num = 0)

Name: DMAC_SADDR0

Access: read-write

Address: 0x400B003C

31 30 29 28 27 26 25 24
SADDR
23 22 21 20 19 18 17 16
SADDR
15 14 13 12 11 10 9 8
SADDR
7 6 5 4 3 2 1 0
SADDR

DMAC DMAC Channel Destination Address Register (ch_num = 0)

Name: DMAC_DADDR0

Access: read-write

Address: 0x400B0040

31 30 29 28 27 26 25 24
DADDR
23 22 21 20 19 18 17 16
DADDR
15 14 13 12 11 10 9 8
DADDR
7 6 5 4 3 2 1 0
DADDR

DMAC DMAC Channel Descriptor Address Register (ch_num = 0)

Name: DMAC_DSCR0

Access: read-write

Address: 0x400B0044

31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR
7 6 5 4 3 2 1 0
DSCR - -

DMAC DMAC Channel Control A Register (ch_num = 0)

Name: DMAC_CTRLA0

Access: read-write

Address: 0x400B0048

31 30 29 28 27 26 25 24
DONE - DST_WIDTH - - SRC_WIDTH
23 22 21 20 19 18 17 16
- DCSIZE - SCSIZE
15 14 13 12 11 10 9 8
BTSIZE
7 6 5 4 3 2 1 0
BTSIZE

DMAC DMAC Channel Control B Register (ch_num = 0)

Name: DMAC_CTRLB0

Access: read-write

Address: 0x400B004C

31 30 29 28 27 26 25 24
- IEN DST_INCR - - SRC_INCR
23 22 21 20 19 18 17 16
FC DST_DSCR - - - SRC_DSCR
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -

DMAC DMAC Channel Configuration Register (ch_num = 0)

Name: DMAC_CFG0

Access: read-write

Address: 0x400B0050

31 30 29 28 27 26 25 24
- - FIFOCFG - AHB_PROT
23 22 21 20 19 18 17 16
- LOCK_IF_L LOCK_B LOCK_IF - - - SOD
15 14 13 12 11 10 9 8
- - DST_H2SEL - - - SRC_H2SEL -
7 6 5 4 3 2 1 0
DST_PER SRC_PER

DMAC DMAC Channel Source Address Register (ch_num = 1)

Name: DMAC_SADDR1

Access: read-write

Address: 0x400B0064

31 30 29 28 27 26 25 24
SADDR
23 22 21 20 19 18 17 16
SADDR
15 14 13 12 11 10 9 8
SADDR
7 6 5 4 3 2 1 0
SADDR

DMAC DMAC Channel Destination Address Register (ch_num = 1)

Name: DMAC_DADDR1

Access: read-write

Address: 0x400B0068

31 30 29 28 27 26 25 24
DADDR
23 22 21 20 19 18 17 16
DADDR
15 14 13 12 11 10 9 8
DADDR
7 6 5 4 3 2 1 0
DADDR

DMAC DMAC Channel Descriptor Address Register (ch_num = 1)

Name: DMAC_DSCR1

Access: read-write

Address: 0x400B006C

31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR
7 6 5 4 3 2 1 0
DSCR - -

DMAC DMAC Channel Control A Register (ch_num = 1)

Name: DMAC_CTRLA1

Access: read-write

Address: 0x400B0070

31 30 29 28 27 26 25 24
DONE - DST_WIDTH - - SRC_WIDTH
23 22 21 20 19 18 17 16
- DCSIZE - SCSIZE
15 14 13 12 11 10 9 8
BTSIZE
7 6 5 4 3 2 1 0
BTSIZE

DMAC DMAC Channel Control B Register (ch_num = 1)

Name: DMAC_CTRLB1

Access: read-write

Address: 0x400B0074

31 30 29 28 27 26 25 24
- IEN DST_INCR - - SRC_INCR
23 22 21 20 19 18 17 16
FC DST_DSCR - - - SRC_DSCR
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -

DMAC DMAC Channel Configuration Register (ch_num = 1)

Name: DMAC_CFG1

Access: read-write

Address: 0x400B0078

31 30 29 28 27 26 25 24
- - FIFOCFG - AHB_PROT
23 22 21 20 19 18 17 16
- LOCK_IF_L LOCK_B LOCK_IF - - - SOD
15 14 13 12 11 10 9 8
- - DST_H2SEL - - - SRC_H2SEL -
7 6 5 4 3 2 1 0
DST_PER SRC_PER

DMAC DMAC Channel Source Address Register (ch_num = 2)

Name: DMAC_SADDR2

Access: read-write

Address: 0x400B008C

31 30 29 28 27 26 25 24
SADDR
23 22 21 20 19 18 17 16
SADDR
15 14 13 12 11 10 9 8
SADDR
7 6 5 4 3 2 1 0
SADDR

DMAC DMAC Channel Destination Address Register (ch_num = 2)

Name: DMAC_DADDR2

Access: read-write

Address: 0x400B0090

31 30 29 28 27 26 25 24
DADDR
23 22 21 20 19 18 17 16
DADDR
15 14 13 12 11 10 9 8
DADDR
7 6 5 4 3 2 1 0
DADDR

DMAC DMAC Channel Descriptor Address Register (ch_num = 2)

Name: DMAC_DSCR2

Access: read-write

Address: 0x400B0094

31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR
7 6 5 4 3 2 1 0
DSCR - -

DMAC DMAC Channel Control A Register (ch_num = 2)

Name: DMAC_CTRLA2

Access: read-write

Address: 0x400B0098

31 30 29 28 27 26 25 24
DONE - DST_WIDTH - - SRC_WIDTH
23 22 21 20 19 18 17 16
- DCSIZE - SCSIZE
15 14 13 12 11 10 9 8
BTSIZE
7 6 5 4 3 2 1 0
BTSIZE

DMAC DMAC Channel Control B Register (ch_num = 2)

Name: DMAC_CTRLB2

Access: read-write

Address: 0x400B009C

31 30 29 28 27 26 25 24
- IEN DST_INCR - - SRC_INCR
23 22 21 20 19 18 17 16
FC DST_DSCR - - - SRC_DSCR
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -

DMAC DMAC Channel Configuration Register (ch_num = 2)

Name: DMAC_CFG2

Access: read-write

Address: 0x400B00A0

31 30 29 28 27 26 25 24
- - FIFOCFG - AHB_PROT
23 22 21 20 19 18 17 16
- LOCK_IF_L LOCK_B LOCK_IF - - - SOD
15 14 13 12 11 10 9 8
- - DST_H2SEL - - - SRC_H2SEL -
7 6 5 4 3 2 1 0
DST_PER SRC_PER

DMAC DMAC Channel Source Address Register (ch_num = 3)

Name: DMAC_SADDR3

Access: read-write

Address: 0x400B00B4

31 30 29 28 27 26 25 24
SADDR
23 22 21 20 19 18 17 16
SADDR
15 14 13 12 11 10 9 8
SADDR
7 6 5 4 3 2 1 0
SADDR

DMAC DMAC Channel Destination Address Register (ch_num = 3)

Name: DMAC_DADDR3

Access: read-write

Address: 0x400B00B8

31 30 29 28 27 26 25 24
DADDR
23 22 21 20 19 18 17 16
DADDR
15 14 13 12 11 10 9 8
DADDR
7 6 5 4 3 2 1 0
DADDR

DMAC DMAC Channel Descriptor Address Register (ch_num = 3)

Name: DMAC_DSCR3

Access: read-write

Address: 0x400B00BC

31 30 29 28 27 26 25 24
DSCR
23 22 21 20 19 18 17 16
DSCR
15 14 13 12 11 10 9 8
DSCR
7 6 5 4 3 2 1 0
DSCR - -

DMAC DMAC Channel Control A Register (ch_num = 3)

Name: DMAC_CTRLA3

Access: read-write

Address: 0x400B00C0

31 30 29 28 27 26 25 24
DONE - DST_WIDTH - - SRC_WIDTH
23 22 21 20 19 18 17 16
- DCSIZE - SCSIZE
15 14 13 12 11 10 9 8
BTSIZE
7 6 5 4 3 2 1 0
BTSIZE

DMAC DMAC Channel Control B Register (ch_num = 3)

Name: DMAC_CTRLB3

Access: read-write

Address: 0x400B00C4

31 30 29 28 27 26 25 24
- IEN DST_INCR - - SRC_INCR
23 22 21 20 19 18 17 16
FC DST_DSCR - - - SRC_DSCR
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - - - - - - -

DMAC DMAC Channel Configuration Register (ch_num = 3)

Name: DMAC_CFG3

Access: read-write

Address: 0x400B00C8

31 30 29 28 27 26 25 24
- - FIFOCFG - AHB_PROT
23 22 21 20 19 18 17 16
- LOCK_IF_L LOCK_B LOCK_IF - - - SOD
15 14 13 12 11 10 9 8
- - DST_H2SEL - - - SRC_H2SEL -
7 6 5 4 3 2 1 0
DST_PER SRC_PER

DMAC DMAC Write Protect Mode Register

Name: DMAC_WPMR

Access: read-write

Address: 0x400B01E4

31 30 29 28 27 26 25 24
WPKEY
23 22 21 20 19 18 17 16
WPKEY
15 14 13 12 11 10 9 8
WPKEY
7 6 5 4 3 2 1 0
- - - - - - - WPEN

DMAC DMAC Write Protect Status Register

Name: DMAC_WPSR

Access: read-only

Address: 0x400B01E8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
WPVSRC
15 14 13 12 11 10 9 8
WPVSRC
7 6 5 4 3 2 1 0
- - - - - - - WPVS