SAM3U UDPHS

USB High Speed Device Port (UDPHS) User Interface

Registers

Register Mapping
Address Register Name Access Reset
0x400A4000 UDPHS Control Register UDPHS_CTRL read-write 0x00000200
0x400A4004 UDPHS Frame Number Register UDPHS_FNUM read-only 0x00000000
0x400A4010 UDPHS Interrupt Enable Register UDPHS_IEN read-write 0x00000010
0x400A4014 UDPHS Interrupt Status Register UDPHS_INTSTA read-only 0x00000000
0x400A4018 UDPHS Clear Interrupt Register UDPHS_CLRINT write-only -
0x400A401C UDPHS Endpoints Reset Register UDPHS_EPTRST write-only -
0x400A40E0 UDPHS Test Register UDPHS_TST read-write 0x00000000
0x400A40F0 UDPHS Name1 Register UDPHS_IPNAME1 read-only 0x48555342
0x400A40F4 UDPHS Name2 Register UDPHS_IPNAME2 read-only 0x32444556
0x400A40F8 UDPHS Features Register UDPHS_IPFEATURES read-only -
0x400A4100 UDPHS Endpoint Configuration Register (endpoint = 0) UDPHS_EPTCFG0 read-write 0x00000000
0x400A4104 UDPHS Endpoint Control Enable Register (endpoint = 0) UDPHS_EPTCTLENB0 write-only -
0x400A4108 UDPHS Endpoint Control Disable Register (endpoint = 0) UDPHS_EPTCTLDIS0 write-only -
0x400A410C UDPHS Endpoint Control Register (endpoint = 0) UDPHS_EPTCTL0 read-only 0x00000000
0x400A4114 UDPHS Endpoint Set Status Register (endpoint = 0) UDPHS_EPTSETSTA0 write-only -
0x400A4118 UDPHS Endpoint Clear Status Register (endpoint = 0) UDPHS_EPTCLRSTA0 write-only -
0x400A411C UDPHS Endpoint Status Register (endpoint = 0) UDPHS_EPTSTA0 read-only 0x00000040
0x400A4120 UDPHS Endpoint Configuration Register (endpoint = 1) UDPHS_EPTCFG1 read-write 0x00000000
0x400A4124 UDPHS Endpoint Control Enable Register (endpoint = 1) UDPHS_EPTCTLENB1 write-only -
0x400A4128 UDPHS Endpoint Control Disable Register (endpoint = 1) UDPHS_EPTCTLDIS1 write-only -
0x400A412C UDPHS Endpoint Control Register (endpoint = 1) UDPHS_EPTCTL1 read-only 0x00000000
0x400A4134 UDPHS Endpoint Set Status Register (endpoint = 1) UDPHS_EPTSETSTA1 write-only -
0x400A4138 UDPHS Endpoint Clear Status Register (endpoint = 1) UDPHS_EPTCLRSTA1 write-only -
0x400A413C UDPHS Endpoint Status Register (endpoint = 1) UDPHS_EPTSTA1 read-only 0x00000040
0x400A4140 UDPHS Endpoint Configuration Register (endpoint = 2) UDPHS_EPTCFG2 read-write 0x00000000
0x400A4144 UDPHS Endpoint Control Enable Register (endpoint = 2) UDPHS_EPTCTLENB2 write-only -
0x400A4148 UDPHS Endpoint Control Disable Register (endpoint = 2) UDPHS_EPTCTLDIS2 write-only -
0x400A414C UDPHS Endpoint Control Register (endpoint = 2) UDPHS_EPTCTL2 read-only 0x00000000
0x400A4154 UDPHS Endpoint Set Status Register (endpoint = 2) UDPHS_EPTSETSTA2 write-only -
0x400A4158 UDPHS Endpoint Clear Status Register (endpoint = 2) UDPHS_EPTCLRSTA2 write-only -
0x400A415C UDPHS Endpoint Status Register (endpoint = 2) UDPHS_EPTSTA2 read-only 0x00000040
0x400A4160 UDPHS Endpoint Configuration Register (endpoint = 3) UDPHS_EPTCFG3 read-write 0x00000000
0x400A4164 UDPHS Endpoint Control Enable Register (endpoint = 3) UDPHS_EPTCTLENB3 write-only -
0x400A4168 UDPHS Endpoint Control Disable Register (endpoint = 3) UDPHS_EPTCTLDIS3 write-only -
0x400A416C UDPHS Endpoint Control Register (endpoint = 3) UDPHS_EPTCTL3 read-only 0x00000000
0x400A4174 UDPHS Endpoint Set Status Register (endpoint = 3) UDPHS_EPTSETSTA3 write-only -
0x400A4178 UDPHS Endpoint Clear Status Register (endpoint = 3) UDPHS_EPTCLRSTA3 write-only -
0x400A417C UDPHS Endpoint Status Register (endpoint = 3) UDPHS_EPTSTA3 read-only 0x00000040
0x400A4180 UDPHS Endpoint Configuration Register (endpoint = 4) UDPHS_EPTCFG4 read-write 0x00000000
0x400A4184 UDPHS Endpoint Control Enable Register (endpoint = 4) UDPHS_EPTCTLENB4 write-only -
0x400A4188 UDPHS Endpoint Control Disable Register (endpoint = 4) UDPHS_EPTCTLDIS4 write-only -
0x400A418C UDPHS Endpoint Control Register (endpoint = 4) UDPHS_EPTCTL4 read-only 0x00000000
0x400A4194 UDPHS Endpoint Set Status Register (endpoint = 4) UDPHS_EPTSETSTA4 write-only -
0x400A4198 UDPHS Endpoint Clear Status Register (endpoint = 4) UDPHS_EPTCLRSTA4 write-only -
0x400A419C UDPHS Endpoint Status Register (endpoint = 4) UDPHS_EPTSTA4 read-only 0x00000040
0x400A41A0 UDPHS Endpoint Configuration Register (endpoint = 5) UDPHS_EPTCFG5 read-write 0x00000000
0x400A41A4 UDPHS Endpoint Control Enable Register (endpoint = 5) UDPHS_EPTCTLENB5 write-only -
0x400A41A8 UDPHS Endpoint Control Disable Register (endpoint = 5) UDPHS_EPTCTLDIS5 write-only -
0x400A41AC UDPHS Endpoint Control Register (endpoint = 5) UDPHS_EPTCTL5 read-only 0x00000000
0x400A41B4 UDPHS Endpoint Set Status Register (endpoint = 5) UDPHS_EPTSETSTA5 write-only -
0x400A41B8 UDPHS Endpoint Clear Status Register (endpoint = 5) UDPHS_EPTCLRSTA5 write-only -
0x400A41BC UDPHS Endpoint Status Register (endpoint = 5) UDPHS_EPTSTA5 read-only 0x00000040
0x400A41C0 UDPHS Endpoint Configuration Register (endpoint = 6) UDPHS_EPTCFG6 read-write 0x00000000
0x400A41C4 UDPHS Endpoint Control Enable Register (endpoint = 6) UDPHS_EPTCTLENB6 write-only -
0x400A41C8 UDPHS Endpoint Control Disable Register (endpoint = 6) UDPHS_EPTCTLDIS6 write-only -
0x400A41CC UDPHS Endpoint Control Register (endpoint = 6) UDPHS_EPTCTL6 read-only 0x00000000
0x400A41D4 UDPHS Endpoint Set Status Register (endpoint = 6) UDPHS_EPTSETSTA6 write-only -
0x400A41D8 UDPHS Endpoint Clear Status Register (endpoint = 6) UDPHS_EPTCLRSTA6 write-only -
0x400A41DC UDPHS Endpoint Status Register (endpoint = 6) UDPHS_EPTSTA6 read-only 0x00000040
0x400A4300 UDPHS DMA Next Descriptor Address Register (channel = 0) UDPHS_DMANXTDSC0 read-write 0x00000000
0x400A4304 UDPHS DMA Channel Address Register (channel = 0) UDPHS_DMAADDRESS0 read-write 0x00000000
0x400A4308 UDPHS DMA Channel Control Register (channel = 0) UDPHS_DMACONTROL0 read-write 0x00000000
0x400A430C UDPHS DMA Channel Status Register (channel = 0) UDPHS_DMASTATUS0 read-write 0x00000000
0x400A4310 UDPHS DMA Next Descriptor Address Register (channel = 1) UDPHS_DMANXTDSC1 read-write 0x00000000
0x400A4314 UDPHS DMA Channel Address Register (channel = 1) UDPHS_DMAADDRESS1 read-write 0x00000000
0x400A4318 UDPHS DMA Channel Control Register (channel = 1) UDPHS_DMACONTROL1 read-write 0x00000000
0x400A431C UDPHS DMA Channel Status Register (channel = 1) UDPHS_DMASTATUS1 read-write 0x00000000
0x400A4320 UDPHS DMA Next Descriptor Address Register (channel = 2) UDPHS_DMANXTDSC2 read-write 0x00000000
0x400A4324 UDPHS DMA Channel Address Register (channel = 2) UDPHS_DMAADDRESS2 read-write 0x00000000
0x400A4328 UDPHS DMA Channel Control Register (channel = 2) UDPHS_DMACONTROL2 read-write 0x00000000
0x400A432C UDPHS DMA Channel Status Register (channel = 2) UDPHS_DMASTATUS2 read-write 0x00000000
0x400A4330 UDPHS DMA Next Descriptor Address Register (channel = 3) UDPHS_DMANXTDSC3 read-write 0x00000000
0x400A4334 UDPHS DMA Channel Address Register (channel = 3) UDPHS_DMAADDRESS3 read-write 0x00000000
0x400A4338 UDPHS DMA Channel Control Register (channel = 3) UDPHS_DMACONTROL3 read-write 0x00000000
0x400A433C UDPHS DMA Channel Status Register (channel = 3) UDPHS_DMASTATUS3 read-write 0x00000000
0x400A4340 UDPHS DMA Next Descriptor Address Register (channel = 4) UDPHS_DMANXTDSC4 read-write 0x00000000
0x400A4344 UDPHS DMA Channel Address Register (channel = 4) UDPHS_DMAADDRESS4 read-write 0x00000000
0x400A4348 UDPHS DMA Channel Control Register (channel = 4) UDPHS_DMACONTROL4 read-write 0x00000000
0x400A434C UDPHS DMA Channel Status Register (channel = 4) UDPHS_DMASTATUS4 read-write 0x00000000
0x400A4350 UDPHS DMA Next Descriptor Address Register (channel = 5) UDPHS_DMANXTDSC5 read-write 0x00000000
0x400A4354 UDPHS DMA Channel Address Register (channel = 5) UDPHS_DMAADDRESS5 read-write 0x00000000
0x400A4358 UDPHS DMA Channel Control Register (channel = 5) UDPHS_DMACONTROL5 read-write 0x00000000
0x400A435C UDPHS DMA Channel Status Register (channel = 5) UDPHS_DMASTATUS5 read-write 0x00000000

Register Fields

UDPHS UDPHS Control Register

Name: UDPHS_CTRL

Access: read-write

Address: 0x400A4000

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - PULLD_DIS REWAKEUP DETACH EN_UDPHS
7 6 5 4 3 2 1 0
FADDR_EN DEV_ADDR

UDPHS UDPHS Frame Number Register

Name: UDPHS_FNUM

Access: read-only

Address: 0x400A4004

31 30 29 28 27 26 25 24
FNUM_ERR - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - FRAME_NUMBER
7 6 5 4 3 2 1 0
FRAME_NUMBER MICRO_FRAME_NUM

UDPHS UDPHS Interrupt Enable Register

Name: UDPHS_IEN

Access: read-write

Address: 0x400A4010

31 30 29 28 27 26 25 24
- DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- EPT_6 EPT_5 EPT_4 EPT_3 EPT_2 EPT_1 EPT_0
7 6 5 4 3 2 1 0
UPSTR_RES ENDOFRSM WAKE_UP ENDRESET INT_SOF MICRO_SOF DET_SUSPD -

UDPHS UDPHS Interrupt Status Register

Name: UDPHS_INTSTA

Access: read-only

Address: 0x400A4014

31 30 29 28 27 26 25 24
- DMA_6 DMA_5 DMA_4 DMA_3 DMA_2 DMA_1 -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- EPT_6 EPT_5 EPT_4 EPT_3 EPT_2 EPT_1 EPT_0
7 6 5 4 3 2 1 0
UPSTR_RES ENDOFRSM WAKE_UP ENDRESET INT_SOF MICRO_SOF DET_SUSPD SPEED

UDPHS UDPHS Clear Interrupt Register

Name: UDPHS_CLRINT

Access: write-only

Address: 0x400A4018

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
UPSTR_RES ENDOFRSM WAKE_UP ENDRESET INT_SOF MICRO_SOF DET_SUSPD -

UDPHS UDPHS Endpoints Reset Register

Name: UDPHS_EPTRST

Access: write-only

Address: 0x400A401C

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- EPT_6 EPT_5 EPT_4 EPT_3 EPT_2 EPT_1 EPT_0

UDPHS UDPHS Test Register

Name: UDPHS_TST

Access: read-write

Address: 0x400A40E0

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- - OPMODE2 TST_PKT TST_K TST_J SPEED_CFG

UDPHS UDPHS Name1 Register

Name: UDPHS_IPNAME1

Access: read-only

Address: 0x400A40F0

31 30 29 28 27 26 25 24
IP_NAME1
23 22 21 20 19 18 17 16
IP_NAME1
15 14 13 12 11 10 9 8
IP_NAME1
7 6 5 4 3 2 1 0
IP_NAME1

UDPHS UDPHS Name2 Register

Name: UDPHS_IPNAME2

Access: read-only

Address: 0x400A40F4

31 30 29 28 27 26 25 24
IP_NAME2
23 22 21 20 19 18 17 16
IP_NAME2
15 14 13 12 11 10 9 8
IP_NAME2
7 6 5 4 3 2 1 0
IP_NAME2

UDPHS UDPHS Features Register

Name: UDPHS_IPFEATURES

Access: read-only

Address: 0x400A40F8

31 30 29 28 27 26 25 24
ISO_EPT_15 ISO_EPT_14 ISO_EPT_13 ISO_EPT_12 ISO_EPT_11 ISO_EPT_10 ISO_EPT_9 ISO_EPT_8
23 22 21 20 19 18 17 16
ISO_EPT_7 ISO_EPT_6 ISO_EPT_5 ISO_EPT_4 ISO_EPT_3 ISO_EPT_2 ISO_EPT_1 DATAB16_8
15 14 13 12 11 10 9 8
BW_DPRAM FIFO_MAX_SIZE DMA_FIFO_WORD_DEPTH
7 6 5 4 3 2 1 0
DMA_B_SIZ DMA_CHANNEL_NBR EPT_NBR_MAX

UDPHS UDPHS Endpoint Configuration Register (endpoint = 0)

Name: UDPHS_EPTCFG0

Access: read-write

Address: 0x400A4100

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 0)

Name: UDPHS_EPTCTLENB0

Access: write-only

Address: 0x400A4104

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 0)

Name: UDPHS_EPTCTLDIS0

Access: write-only

Address: 0x400A4108

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 0)

Name: UDPHS_EPTCTL0

Access: read-only

Address: 0x400A410C

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 0)

Name: UDPHS_EPTSETSTA0

Access: write-only

Address: 0x400A4114

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 0)

Name: UDPHS_EPTCLRSTA0

Access: write-only

Address: 0x400A4118

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 0)

Name: UDPHS_EPTSTA0

Access: read-only

Address: 0x400A411C

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS Endpoint Configuration Register (endpoint = 1)

Name: UDPHS_EPTCFG1

Access: read-write

Address: 0x400A4120

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 1)

Name: UDPHS_EPTCTLENB1

Access: write-only

Address: 0x400A4124

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 1)

Name: UDPHS_EPTCTLDIS1

Access: write-only

Address: 0x400A4128

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 1)

Name: UDPHS_EPTCTL1

Access: read-only

Address: 0x400A412C

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 1)

Name: UDPHS_EPTSETSTA1

Access: write-only

Address: 0x400A4134

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 1)

Name: UDPHS_EPTCLRSTA1

Access: write-only

Address: 0x400A4138

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 1)

Name: UDPHS_EPTSTA1

Access: read-only

Address: 0x400A413C

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS Endpoint Configuration Register (endpoint = 2)

Name: UDPHS_EPTCFG2

Access: read-write

Address: 0x400A4140

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 2)

Name: UDPHS_EPTCTLENB2

Access: write-only

Address: 0x400A4144

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 2)

Name: UDPHS_EPTCTLDIS2

Access: write-only

Address: 0x400A4148

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 2)

Name: UDPHS_EPTCTL2

Access: read-only

Address: 0x400A414C

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 2)

Name: UDPHS_EPTSETSTA2

Access: write-only

Address: 0x400A4154

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 2)

Name: UDPHS_EPTCLRSTA2

Access: write-only

Address: 0x400A4158

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 2)

Name: UDPHS_EPTSTA2

Access: read-only

Address: 0x400A415C

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS Endpoint Configuration Register (endpoint = 3)

Name: UDPHS_EPTCFG3

Access: read-write

Address: 0x400A4160

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 3)

Name: UDPHS_EPTCTLENB3

Access: write-only

Address: 0x400A4164

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 3)

Name: UDPHS_EPTCTLDIS3

Access: write-only

Address: 0x400A4168

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 3)

Name: UDPHS_EPTCTL3

Access: read-only

Address: 0x400A416C

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 3)

Name: UDPHS_EPTSETSTA3

Access: write-only

Address: 0x400A4174

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 3)

Name: UDPHS_EPTCLRSTA3

Access: write-only

Address: 0x400A4178

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 3)

Name: UDPHS_EPTSTA3

Access: read-only

Address: 0x400A417C

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS Endpoint Configuration Register (endpoint = 4)

Name: UDPHS_EPTCFG4

Access: read-write

Address: 0x400A4180

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 4)

Name: UDPHS_EPTCTLENB4

Access: write-only

Address: 0x400A4184

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 4)

Name: UDPHS_EPTCTLDIS4

Access: write-only

Address: 0x400A4188

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 4)

Name: UDPHS_EPTCTL4

Access: read-only

Address: 0x400A418C

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 4)

Name: UDPHS_EPTSETSTA4

Access: write-only

Address: 0x400A4194

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 4)

Name: UDPHS_EPTCLRSTA4

Access: write-only

Address: 0x400A4198

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 4)

Name: UDPHS_EPTSTA4

Access: read-only

Address: 0x400A419C

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS Endpoint Configuration Register (endpoint = 5)

Name: UDPHS_EPTCFG5

Access: read-write

Address: 0x400A41A0

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 5)

Name: UDPHS_EPTCTLENB5

Access: write-only

Address: 0x400A41A4

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 5)

Name: UDPHS_EPTCTLDIS5

Access: write-only

Address: 0x400A41A8

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 5)

Name: UDPHS_EPTCTL5

Access: read-only

Address: 0x400A41AC

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 5)

Name: UDPHS_EPTSETSTA5

Access: write-only

Address: 0x400A41B4

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 5)

Name: UDPHS_EPTCLRSTA5

Access: write-only

Address: 0x400A41B8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 5)

Name: UDPHS_EPTSTA5

Access: read-only

Address: 0x400A41BC

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS Endpoint Configuration Register (endpoint = 6)

Name: UDPHS_EPTCFG6

Access: read-write

Address: 0x400A41C0

31 30 29 28 27 26 25 24
EPT_MAPD - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - - - NB_TRANS
7 6 5 4 3 2 1 0
BK_NUMBER EPT_TYPE EPT_DIR EPT_SIZE

UDPHS UDPHS Endpoint Control Enable Register (endpoint = 6)

Name: UDPHS_EPTCTLENB6

Access: write-only

Address: 0x400A41C4

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Control Disable Register (endpoint = 6)

Name: UDPHS_EPTCTLDIS6

Access: write-only

Address: 0x400A41C8

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_DISABL

UDPHS UDPHS Endpoint Control Register (endpoint = 6)

Name: UDPHS_EPTCTL6

Access: read-only

Address: 0x400A41CC

31 30 29 28 27 26 25 24
SHRT_PCKT - - - - - - -
23 22 21 20 19 18 17 16
- - - - - BUSY_BANK - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
MDATA_RX DATAX_RX - NYET_DIS INTDIS_DMA - AUTO_VALID EPT_ENABL

UDPHS UDPHS Endpoint Set Status Register (endpoint = 6)

Name: UDPHS_EPTSETSTA6

Access: write-only

Address: 0x400A41D4

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
- - - - TX_PK_RDY - KILL_BANK -
7 6 5 4 3 2 1 0
- - FRCESTALL - - - - -

UDPHS UDPHS Endpoint Clear Status Register (endpoint = 6)

Name: UDPHS_EPTCLRSTA6

Access: write-only

Address: 0x400A41D8

31 30 29 28 27 26 25 24
- - - - - - - -
23 22 21 20 19 18 17 16
- - - - - - - -
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP - TX_COMPLT RX_BK_RDY -
7 6 5 4 3 2 1 0
- TOGGLESQ FRCESTALL - - - - -

UDPHS UDPHS Endpoint Status Register (endpoint = 6)

Name: UDPHS_EPTSTA6

Access: read-only

Address: 0x400A41DC

31 30 29 28 27 26 25 24
SHRT_PCKT BYTE_COUNT
23 22 21 20 19 18 17 16
BYTE_COUNT BUSY_BANK_STA CURRENT_BANK
15 14 13 12 11 10 9 8
NAK_OUT NAK_IN STALL_SNT RX_SETUP TX_PK_RDY TX_COMPLT RX_BK_RDY ERR_OVFLW
7 6 5 4 3 2 1 0
TOGGLESQ_STA FRCESTALL - - - - -

UDPHS UDPHS DMA Next Descriptor Address Register (channel = 0)

Name: UDPHS_DMANXTDSC0

Access: read-write

Address: 0x400A4300

31 30 29 28 27 26 25 24
NXT_DSC_ADD
23 22 21 20 19 18 17 16
NXT_DSC_ADD
15 14 13 12 11 10 9 8
NXT_DSC_ADD
7 6 5 4 3 2 1 0
NXT_DSC_ADD

UDPHS UDPHS DMA Channel Address Register (channel = 0)

Name: UDPHS_DMAADDRESS0

Access: read-write

Address: 0x400A4304

31 30 29 28 27 26 25 24
BUFF_ADD
23 22 21 20 19 18 17 16
BUFF_ADD
15 14 13 12 11 10 9 8
BUFF_ADD
7 6 5 4 3 2 1 0
BUFF_ADD

UDPHS UDPHS DMA Channel Control Register (channel = 0)

Name: UDPHS_DMACONTROL0

Access: read-write

Address: 0x400A4308

31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB

UDPHS UDPHS DMA Channel Status Register (channel = 0)

Name: UDPHS_DMASTATUS0

Access: read-write

Address: 0x400A430C

31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESC_LDST END_BF_ST END_TR_ST - - CHANN_ACT CHANN_ENB

UDPHS UDPHS DMA Next Descriptor Address Register (channel = 1)

Name: UDPHS_DMANXTDSC1

Access: read-write

Address: 0x400A4310

31 30 29 28 27 26 25 24
NXT_DSC_ADD
23 22 21 20 19 18 17 16
NXT_DSC_ADD
15 14 13 12 11 10 9 8
NXT_DSC_ADD
7 6 5 4 3 2 1 0
NXT_DSC_ADD

UDPHS UDPHS DMA Channel Address Register (channel = 1)

Name: UDPHS_DMAADDRESS1

Access: read-write

Address: 0x400A4314

31 30 29 28 27 26 25 24
BUFF_ADD
23 22 21 20 19 18 17 16
BUFF_ADD
15 14 13 12 11 10 9 8
BUFF_ADD
7 6 5 4 3 2 1 0
BUFF_ADD

UDPHS UDPHS DMA Channel Control Register (channel = 1)

Name: UDPHS_DMACONTROL1

Access: read-write

Address: 0x400A4318

31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB

UDPHS UDPHS DMA Channel Status Register (channel = 1)

Name: UDPHS_DMASTATUS1

Access: read-write

Address: 0x400A431C

31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESC_LDST END_BF_ST END_TR_ST - - CHANN_ACT CHANN_ENB

UDPHS UDPHS DMA Next Descriptor Address Register (channel = 2)

Name: UDPHS_DMANXTDSC2

Access: read-write

Address: 0x400A4320

31 30 29 28 27 26 25 24
NXT_DSC_ADD
23 22 21 20 19 18 17 16
NXT_DSC_ADD
15 14 13 12 11 10 9 8
NXT_DSC_ADD
7 6 5 4 3 2 1 0
NXT_DSC_ADD

UDPHS UDPHS DMA Channel Address Register (channel = 2)

Name: UDPHS_DMAADDRESS2

Access: read-write

Address: 0x400A4324

31 30 29 28 27 26 25 24
BUFF_ADD
23 22 21 20 19 18 17 16
BUFF_ADD
15 14 13 12 11 10 9 8
BUFF_ADD
7 6 5 4 3 2 1 0
BUFF_ADD

UDPHS UDPHS DMA Channel Control Register (channel = 2)

Name: UDPHS_DMACONTROL2

Access: read-write

Address: 0x400A4328

31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB

UDPHS UDPHS DMA Channel Status Register (channel = 2)

Name: UDPHS_DMASTATUS2

Access: read-write

Address: 0x400A432C

31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESC_LDST END_BF_ST END_TR_ST - - CHANN_ACT CHANN_ENB

UDPHS UDPHS DMA Next Descriptor Address Register (channel = 3)

Name: UDPHS_DMANXTDSC3

Access: read-write

Address: 0x400A4330

31 30 29 28 27 26 25 24
NXT_DSC_ADD
23 22 21 20 19 18 17 16
NXT_DSC_ADD
15 14 13 12 11 10 9 8
NXT_DSC_ADD
7 6 5 4 3 2 1 0
NXT_DSC_ADD

UDPHS UDPHS DMA Channel Address Register (channel = 3)

Name: UDPHS_DMAADDRESS3

Access: read-write

Address: 0x400A4334

31 30 29 28 27 26 25 24
BUFF_ADD
23 22 21 20 19 18 17 16
BUFF_ADD
15 14 13 12 11 10 9 8
BUFF_ADD
7 6 5 4 3 2 1 0
BUFF_ADD

UDPHS UDPHS DMA Channel Control Register (channel = 3)

Name: UDPHS_DMACONTROL3

Access: read-write

Address: 0x400A4338

31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB

UDPHS UDPHS DMA Channel Status Register (channel = 3)

Name: UDPHS_DMASTATUS3

Access: read-write

Address: 0x400A433C

31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESC_LDST END_BF_ST END_TR_ST - - CHANN_ACT CHANN_ENB

UDPHS UDPHS DMA Next Descriptor Address Register (channel = 4)

Name: UDPHS_DMANXTDSC4

Access: read-write

Address: 0x400A4340

31 30 29 28 27 26 25 24
NXT_DSC_ADD
23 22 21 20 19 18 17 16
NXT_DSC_ADD
15 14 13 12 11 10 9 8
NXT_DSC_ADD
7 6 5 4 3 2 1 0
NXT_DSC_ADD

UDPHS UDPHS DMA Channel Address Register (channel = 4)

Name: UDPHS_DMAADDRESS4

Access: read-write

Address: 0x400A4344

31 30 29 28 27 26 25 24
BUFF_ADD
23 22 21 20 19 18 17 16
BUFF_ADD
15 14 13 12 11 10 9 8
BUFF_ADD
7 6 5 4 3 2 1 0
BUFF_ADD

UDPHS UDPHS DMA Channel Control Register (channel = 4)

Name: UDPHS_DMACONTROL4

Access: read-write

Address: 0x400A4348

31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB

UDPHS UDPHS DMA Channel Status Register (channel = 4)

Name: UDPHS_DMASTATUS4

Access: read-write

Address: 0x400A434C

31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESC_LDST END_BF_ST END_TR_ST - - CHANN_ACT CHANN_ENB

UDPHS UDPHS DMA Next Descriptor Address Register (channel = 5)

Name: UDPHS_DMANXTDSC5

Access: read-write

Address: 0x400A4350

31 30 29 28 27 26 25 24
NXT_DSC_ADD
23 22 21 20 19 18 17 16
NXT_DSC_ADD
15 14 13 12 11 10 9 8
NXT_DSC_ADD
7 6 5 4 3 2 1 0
NXT_DSC_ADD

UDPHS UDPHS DMA Channel Address Register (channel = 5)

Name: UDPHS_DMAADDRESS5

Access: read-write

Address: 0x400A4354

31 30 29 28 27 26 25 24
BUFF_ADD
23 22 21 20 19 18 17 16
BUFF_ADD
15 14 13 12 11 10 9 8
BUFF_ADD
7 6 5 4 3 2 1 0
BUFF_ADD

UDPHS UDPHS DMA Channel Control Register (channel = 5)

Name: UDPHS_DMACONTROL5

Access: read-write

Address: 0x400A4358

31 30 29 28 27 26 25 24
BUFF_LENGTH
23 22 21 20 19 18 17 16
BUFF_LENGTH
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
BURST_LCK DESC_LD_IT END_BUFFIT END_TR_IT END_B_EN END_TR_EN LDNXT_DSC CHANN_ENB

UDPHS UDPHS DMA Channel Status Register (channel = 5)

Name: UDPHS_DMASTATUS5

Access: read-write

Address: 0x400A435C

31 30 29 28 27 26 25 24
BUFF_COUNT
23 22 21 20 19 18 17 16
BUFF_COUNT
15 14 13 12 11 10 9 8
- - - - - - - -
7 6 5 4 3 2 1 0
- DESC_LDST END_BF_ST END_TR_ST - - CHANN_ACT CHANN_ENB